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Layout Considerations
The IRPP3637-06A reference design
PCB layout offers compact design with
minimum parasitics at 600kHz switching
frequency. The board is designed with
4 layers using 1 oz copper weight per
layer. Figures 3a through 3d represent
the layout of each layer. To minimize
the parasitics, the following was
observed:
1. The switch node connection path is
made as short as possible by placing
the output inductor L1 close to the drain
of the synchronous FET inside the dual
SO8 package.
2. The input decoupling 10uF ceramic
capacitor C3, is placed across the drain
of the control FET and the ground pin of
the dual SO8 package. The 1200uF
electrolytic capacitor C1 represents the
input bulk capacitance of the
synchronous buck regulator.
3. A solid ground plane is furnished in
mid-layer 2. The connection of the
signal ground to power ground is done
at a single point in the bottom layer as
shown in figure 3d.
4. The feedback track from the output
V OUT to FB pin of the IC is routed as far
away from noise generating traces as
possible in mid-layer 2 as shown in
figure 3c.
www.irf.com
RD-0604
4
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